The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a dielectric layer and a method for fabricating a capacitor.
As the design rule of dynamic random access memories (DRAM) has decreased, high-k dielectric materials [e.g., zirconium oxide (ZrO2)] have been used instead of the typical oxide/nitride/oxide (ONO) or aluminum oxide (Al2O3) in order to maintain a desired memory capacitance. Solely using the high-k dielectric materials may cause a limitation related to a leakage current characteristic. Thus, a crystalline high-k dielectric material and Al2O3, which is an amorphous low-k dielectric material, are mixed to form a structure of “high-k dielectric material/Al2O3/high-k dielectric material.” Thus, the capacitance and the leakage current characteristics may be satisfied. At this time, the high-k dielectric material is formed at a low temperature and the Al2O3 is formed at a high temperature to improve the capacitance.
FIG. 1 illustrates a cross-sectional view of a structure of a typical cylinder type capacitor. A dielectric layer 12 is formed over cylinder type storage electrodes 11. The dielectric layer 12 includes a first ZrO2 layer 12A, an Al2O3 layer 12B, and a second ZrO2 layer 12C, formed in sequential order. At this time, the Al2O3 layer 12B is formed with a small thickness to improve a dielectric constant characteristic.
However, a spacing distance between the adjacent storage electrodes 11 becomes small due to the large scale of integration in the typical cylinder type capacitor. Thus, the adjacent storage electrodes 11 may become electrically connected while the Al2O3 layer 12B is formed at a high temperature, generating a dual bit failure in a reliability assessment.
FIGS. 2A and 2B illustrate a cross-sectional view and a micrographic view, respectively, of a typical result after an Al2O3 layer is formed. According to the typical method, the Al2O3 layer 12B is formed at a temperature of approximately 400° C. or higher after the first ZrO2 layer 12A is formed. At this time, the first ZrO2 layer 12A and the Al2O3 layer 12B may fill a gap (refer to reference denotation ‘G’) between the adjacent cylinder type storage electrodes 11 and stick together. In this case, the subsequent second ZrO2 layer 12C, functioning as a third dielectric layer, may not be formed in the small gap between the adjacent cylinder type storage electrodes 11.
For instance, in a case of forming the first and second ZrO2 layers 12A and 12C to substantially the same thickness ranging from approximately 50 Å to approximately 55 Å, the cylinder type storage electrodes 11 are isolated by the first ZrO2 layer 12A ranging from approximately 100 Å to approximately 110 Å and the Al2O3 layer 12B having a small thickness ranging from approximately 3 Å to approximately 10 Å after the Al2O3 layer 12B is formed. Thus, the dual bit failure may be generated when a bias increases. That is, a dielectric layer having a small thickness of approximately 120 Å may not be sufficient to reduce electrical connection between adjacent cylinder type bottom electrodes.
Referring to FIG. 2B, in a storage electrode structure disposed in zigzag pattern, adjacent cylinders are stuck together where a spacing distance is small between storage electrodes. That is, a bridge (refer to ‘A’) is observed.